Cisco
ASIC STA Technical Lead
$166K–$308K
San Jose, California, US · Hybrid · Full-time · Posted Oct 19, 2026
- Experience
- Bachelor’s + 8 years, or Master’s + 6 years, or PhD + 3 years of related experience. Preferred: Master’s degree + 15+ years experience.
- Education
- Bachelor’s, Master’s, or PhD; no equivalent-experience alternative stated.
About the job
Leads DFT and static timing analysis (STA) work for networking ASICs across implementation and post-silicon validation, with exposure to physical design signoff.
What you'll do
- Develop and verify timing constraints and support STA activities.
- Drive DFT and quality processes through implementation and post-silicon validation.
- Collaborate across teams and communicate timing analysis; support physical design signoff activities.
What they ask for
- Prior experience with RTL design, CDC/RDC and conformal verification, and SDC development.
- Prior experience developing and verifying timing constraints.
- Programming experience in at least two of Perl, TCL, Python, or Makefile.
Nice to have
- Experience debugging PCIE and TSMC memory timing constraints, or analyzing DFT-mode timing closure.
- Experience with Synopsys TCM/Primetime, Synopsys Fusion/design Compiler, or Tessent.
Pay
$186,900.00 to $267,700.00 USD base salary; $186,900.00 - $307,800.00 USD base salary (New York City Metro Area); $166,300.00 - $274,100.00 USD base salary (Non-Metro New York state & Washington state)
Tools
RTL, CDC/RDC, conformal verification, SDC, Perl, TCL, Python, Makefile
Model-written summary · the original posting is authoritative