Cisco
ASIC Technical Leader- CAD
$166K–$308K
San Jose, California, US · Onsite Only · Full-time · Posted Oct 13, 2026
- Experience
- 8+ years in CAD or test automation for semiconductor designs.
About the job
Owns end-to-end design-for-test (DFT) flow architecture and develops scalable CAD automation for ASIC design, test, and signoff.
What you'll do
- Build and maintain DFT flows and CAD infrastructure spanning RTL, insertion, ATPG, simulation, and reporting.
- Develop LSF-based regression frameworks and use AI-driven automation for log analysis, failure triage, and debug.
- Partner with RTL, Physical Design, and Validation teams to integrate and sign off reusable flows.
What they ask for
- 8+ years of experience in CAD or semiconductor-design test automation.
- Experience applying AI/ML to EDA workflows, such as log analysis, anomaly detection, or predictive insights.
- Experience with EDA DFT tools such as Synopsys TestMAX, Synopsys VCS, or Siemen's Tessent; Tcl, Python, Perl, and shell scripting.
- Experience building automated flows and regression systems in compute-farm environments (LSF or similar), and with SoC integration and cross-functional workflows.
Nice to have
- Familiarity with Python/pandas, dashboards, or visualization tools.
- Experience with large-scale regression and distributed job management, or exposure to STIL and silicon bring-up/debug.
Pay
$186,900.00 to $267,700.00 USD base salary; $186,900.00 - $307,800.00 USD base salary; $166,300.00 - $274,100.00 USD base salary
Tools
Synopsys TestMAX, Synopsys VCS, Siemen's Tessent, Tcl, Python, Perl, LSF, STIL
AI focus
Apply AI/ML to EDA workflows and use AI-driven automation for log analysis, anomaly detection, predictive insights, failure triage, and intelligent debug.
Model-written summary · the original posting is authoritative