Cisco
Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)
$166K–$308K
San Jose, California, US +10 · Remote · Full-time · Posted Oct 14, 2026
- Location
- San Jose, California, US
Houston, Texas, US
San Francisco, California, US
Denver, Colorado, US
Boston, Massachusetts, US
Allentown, Pennsylvania, US
Dallas, Texas, US
Atlanta, Georgia, US
Boise, Idaho, US
Cary, North Carolina, US
San Diego, California, US - Experience
- 8+ years with a bachelor's degree, 6+ years with a master's degree, or 3+ years with a PhD in relevant signal and power integrity experience.
- Education
- Bachelor's, Master's, or PhD in Electrical Engineering.
About the job
Leads signal and power integrity simulation and ASIC package design, verification, and release for high-performance Cisco platforms.
What you'll do
- Develop design rules and processes for high-speed signaling and complex ASIC/package development.
- Analyze SI/PI across interposer, substrate, and PCB; collaborate with layout teams, vendors, and system partners to resolve technical issues.
- Lead or contribute to ASIC architecture and design, mentor engineers, and promote design reviews and continuous improvement.
What they ask for
- Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years, or PhD in Electrical Engineering and 3+ years.
- Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
- Experience with pre- and post-layout SI/PI simulations using industry-standard EDA tools.
- Experience conducting layout reviews and physical design validation, and experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
Nice to have
- Experience with HBM or high-speed memory interface SI; die-to-die interfaces (UCIe or proprietary); advanced packaging, including SI/PI analysis of 2.5D ASIC packaging.
- Experience with Vector Network Analysis or IBIS; skilled in communicating technical concepts to diverse audiences.
Pay
$186,900.00 to $267,700.00 USD base salary; $186,900.00 - $307,800.00 USD base salary; $166,300.00 - $274,100.00 USD base salary
Tools
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM flows, SPICE, 56G PAM4 SerDes, UCIe
Model-written summary · the original posting is authoritative