Cisco
High-Speed SerDes Design Engineer - Acacia (Hybrid)
$151K–$282K
San Jose, California, US · Hybrid · Full-time · Posted Aug 28, 2026
- Experience
- Bachelor’s + 8 years, or Master’s + 6 years, or PhD + 3 years of related experience.
- Education
- Bachelor’s, Master’s, or PhD; no equivalent-experience alternative stated.
About the job
Designs, lays out, measures, and productizes high-speed analog and mixed-signal CMOS ICs for optical communications products.
What you'll do
- Architect, design, lay out, measure, and productize high-speed IC designs.
- Lead a large chip block, mentor team members, track deliverables, and participate in design reviews.
- Collaborate with packaging and hardware teams to meet signal and power integrity specifications.
What they ask for
- Bachelor’s degree plus 8 years, master’s degree plus 6 years, or PhD plus 3 years of related experience.
- Design, simulation, and measurement experience in at least 3 listed high-speed IC areas, such as serial links, output drivers, PLLs, or equalization.
Nice to have
- Electrical transceiver application experience, including backplane and cable communications.
- Experience with FinFET or GAA technologies; high-frequency layout; design for manufacturability; lab validation; or listed design software.
Pay
$171,600.00 to $245,000.00 USD (base salary); $171,600.00 - $281,800.00 USD (base salary); $151,300.00 - $250,900.00 USD (base salary)
Tools
CMOS, FinFET, GAA, Cadence (Virtuoso), Specture/APS/SpectreX, Calibre, EMX, Matlab
Model-written summary · the original posting is authoritative