Cisco
Senior Analog Layout Engineer
$149K–$282K
Carlsbad, California, US +1 · Hybrid · Senior · Full-time · Posted Oct 7, 2026
- Location
- Carlsbad, California, US
Allentown, Pennsylvania, US - Experience
- Bachelor’s + 7 years, or Master’s + 4 years, or PhD + 1 year of related experience.
- Education
- Bachelor’s, Master’s, or PhD; no equivalent-experience alternative stated.
About the job
Owns analog and mixed-signal physical layout and integration for next-generation optical silicon, from floorplanning through tapeout and post-silicon bring-up.
What you'll do
- Build and optimize analog and mixed-signal layouts for 100G–400G/lambda optical solutions.
- Drive layout execution through extraction, sign-off, tapeout, and post-silicon bring-up.
- Develop design methodologies, mentor engineers, and address parasitic, signal-integrity, and thermal tradeoffs.
What they ask for
- Bachelor’s + 7 years, or Master’s + 4 years, or PhD + 1 year of related experience.
- Experience supporting block-level layout through tapeout.
- Physical verification and custom analog layout experience in FINFET 7nm, 5nm, or 3nm.
- Experience with Cadence Virtuoso or similar custom layout tools.
Nice to have
- Experience with device-level layout techniques, physical signoff flows, and custom analog layout in TSMC 2nm or below.
- ASIC/SoC tapeout experience, scripting with Python, Perl, or TCL, and collaboration across multi-location teams.
Pay
$149,100.00 to $218,100.00 (base salary); $167,700.00 - $282,000.00 (base salary); $149,100.00 - $250,900.00 (base salary)
Tools
Cadence Virtuoso, Calibre, Linux, Python, Perl, TCL, FINFET 7nm, 5nm
Model-written summary · the original posting is authoritative