Cisco
Senior ASIC Design Verification Engineer
$149K–$282K
San Jose, California, US · Onsite Only · Senior · Full-time · Posted Oct 21, 2026
- Experience
- 7 years of relevant technical experience with a bachelor’s degree, or 4 years with a master’s degree.
- Education
- Bachelor’s degree in Computer, Electrical, or Electronics Engineering, or a master’s degree.
About the job
Defines and verifies ASICs and ASIC subsystems for Cisco platforms, leading verification architecture, implementation, coverage, debugging, and validation.
What you'll do
- Architect and maintain cluster- and chip-level design verification environments, test plans, tests, and reusable verification code.
- Lead verification work, resolve design issues, review architecture, and ensure code and functional coverage.
- Qualify RTL through gate-level simulation and emulation, and support debugging, lab bring-up, and post-silicon validation.
What they ask for
- Bachelor’s degree in Computer, Electrical, or Electronics Engineering plus 7 years of relevant technical experience, or a master’s degree plus 4 years, focused on ASIC design and verification.
- Experience with OOP concepts and SystemVerilog or UVM methodology.
- Experience leading verification teams, assignments, or projects.
- Scripting experience using Perl and/or Python.
Nice to have
- Experience with forwarding logic, parsers, or P4; emulation platforms such as Veloce, Palladium, Zebu, or HAPS; or formal verification tools such as IEV or VC Formal.
- Domain knowledge in one or more of PCIe, CXL, Ethernet, RDMA, DDR, or TCP.
Pay
USD $167,700.00 to $245,200.00 base salary; USD $167,700.00 - $282,000.00 base salary (New York City Metro Area); USD $149,100.00 - $250,900.00 base salary (Non-Metro New York state & Washington state)
Tools
ASIC, SystemVerilog, UVM, Perl, Python, Veloce, Palladium, P4
Model-written summary · the original posting is authoritative