Cisco
Senior ASIC DFT DV Engineer (Hybrid)
$149K–$282K
San Jose, California, US · Hybrid · Senior · Full-time · Posted Oct 13, 2026
- Experience
- At least 7+ years with a bachelor's degree, or 4+ years with a master's degree.
- Education
- Bachelor’s in Electrical Engineering or equivalent.
About the job
Verifies Design-for-Test architectures and owns memory-testing methodology for Cisco Silicon One hardware platforms.
What you'll do
- Plan tests and develop test benches to verify DFT architecture for ATE screening, in-system testing, debug, and diagnostics.
- Own MBIST methodology and build reusable, hierarchical verification infrastructure across large designs.
- Collaborate with RTL and physical design teams to understand chip architecture and drive DFT verification quality.
What they ask for
- Test planning based on complex design specifications.
- Debugging experience using DVE/Verdi.
- Experience with memory architectures such as SRAM or DRAM and their failure modes.
- Experience with TCL, Python, or Perl.
Nice to have
- Experience in Verilog/SV, production memory-failure correlation, or silicon testing and ATE.
- Experience with industry-standard DFT tools such as Synopsys DesignWare, SMS, TestMax, or Mentor Graphics Tessent.
Pay
$167,700.00 to $245,200.00 USD base salary; $167,700.00 - $282,000.00 USD base salary (New York City Metro Area); $149,100.00 - $250,900.00 USD base salary (Non-Metro New York state & Washington state)
Tools
DVE/Verdi, TCL, Python, Perl, Verilog/SV, Synopsys DesignWare, SMS, TestMax
Model-written summary · the original posting is authoritative