Cisco
Senior ASIC DFT DV Engineer (Hybrid)
$149K–$282K
San Jose, California, US +1 · Hybrid · Senior · Full-time · Posted Oct 14, 2026
- Location
- San Jose, California, US
Austin, Texas, US - Experience
- Bachelor’s: at least 7 years; Master’s: at least 4 years.
- Education
- Bachelor’s in Electrical Engineering or equivalent.
About the job
Develops and validates DFT test strategies, test plans, and test benches for silicon designs, supporting manufacturing screening, in-system testing, debug, and post-silicon validation.
What you'll do
- Plan and develop test benches to verify DFT architecture for ATE screening, in-system test, debug, and diagnostics.
- Collaborate with design, design-verification, and physical-design teams to integrate and validate test logic throughout implementation and post-silicon validation.
- Develop reusable hardware DFT and test methodologies for new silicon device models, bare die, and stacked die.
What they ask for
- Bachelor’s in Electrical Engineering or equivalent, or a Master’s degree.
- Experience in test planning based on complex design specifications.
- Testbench development using System Verilog.
- Debugging with DVE/Verdi and experience with TCL, Python, or Perl.
Nice to have
- UVM and advanced System Verilog knowledge.
- Knowledge of JTAG protocol, scan architecture, MBIST, and boundary scan.
Pay
$167,700.00 to $245,200.00 USD base salary; $167,700.00 - $282,000.00 USD base salary; $149,100.00 - $250,900.00 USD base salary
Tools
System Verilog, DVE, Verdi, TCL, Python, Perl, UVM, JTAG
Model-written summary · the original posting is authoritative