Cisco
Senior ASIC Engineer
$149K–$282K
San Jose, California, US · Onsite Only · Senior · Full-time · Posted Sep 4, 2026
- Experience
- Bachelor’s + 7 years of related experience, or Master’s + 4 years, or PhD + 2 years.
- Education
- Bachelor’s, Master’s, or PhD.
About the job
Defines, designs, verifies, and debugs high-performance ASICs, leading block-level design and verification and contributing to chip-level resolution, lab bring-up, and power-saving solutions.
What you'll do
- Own ASIC architecture, design, and verification for complex or multiple functional areas; develop reusable code and verification methodologies.
- Lead design and verification work, reviews, and code reviews; debug issues across ASIC, software, and hardware.
- Support lab bring-up and implement power-saving solutions.
What they ask for
- Experience with ASIC design and verification processes, including System Verilog, debugging, methodology, and tools.
Nice to have
- Experience with regression and coverage dashboards, post-silicon lab bring-up, or UVM verification leadership.
- Experience with emulation platforms (Veloce, Palladium, Zebu, or HAPS), Linux, C/C++, Python/Perl, or networking.
Pay
$167,700.00 to $245,200.00 USD (starting salary); $167,700.00 - $282,000.00 USD (full salary range, New York City Metro Area); $149,100.00 - $250,900.00 USD (full salary range, non-metro New York state & Washington state)
Tools
System Verilog, UVM, Veloce, Palladium, Zebu, HAPS, Linux, C/C++
Model-written summary · the original posting is authoritative