Cisco
Senior ASIC Physical Design Engineering Technical Lead
$192K–$356K
San Jose, California, US +1 · Onsite Only · Senior · Full-time · Posted Oct 27, 2026
- Location
- San Jose, California, US
Austin, Texas, US - Experience
- 12+ years with a Bachelor’s Degree, 8+ years with a Master’s Degree, or 5+ years with a PhD; Physical Design experience.
- Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering.
About the job
Leads ASIC physical design implementation and methodology from RTL to GDSII, optimizing performance and die size and supporting timing and sign-off.
What you'll do
- Lead RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, timing analysis, power integrity, and equivalence checks.
- Improve design tools and flows, guide clock-tree synthesis strategies, and collaborate with design, implementation, EDA, and flow teams.
- Execute timing setup, convergence, sign-off, and functional and timing ECOs across multi-mode, multi-corner scenarios.
What they ask for
- Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience, Master’s Degree in Electrical Engineering with 8+ years, or PhD in Electrical Engineering with 5+ years.
- Experience working on Fullchip activities.
- Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
- Experience with EDA tools like Innovus, Primetime/Tempus, Redhawk/Voltus and Calibre.
Nice to have
- Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
- Experience with Python, TCL, or Perl programming.
Pay
$214,100.00 to $309,800.00 USD base salary; $214,100.00 - $356,300.00 USD base salary (New York City Metro Area); $192,400.00 - $317,200.00 USD base salary (Non-Metro New York state & Washington state)
Tools
Innovus, Primetime/Tempus, Redhawk/Voltus, Calibre, Python, TCL, Perl
Model-written summary · the original posting is authoritative