Cisco
Senior ASIC RTL Engineer
$149K–$282K
San Jose, California, US +1 · Hybrid · Senior · Full-time · Posted Oct 19, 2026
- Location
- San Jose, California, US
Austin, Texas, US - Experience
- At least 7 years.
- Education
- Bachelor's or a Master's Degree in Electrical or Computer Engineering required.
About the job
Develops high-quality Design for Test (DFT) RTL for Cisco Silicon One chips, collaborating with RTL and physical design teams to deliver reliable networking silicon.
What you'll do
- Create DFT RTL and support reliable silicon solutions.
- Collaborate with front-end RTL and backend physical design teams to understand chip architecture.
- Contribute to silicon development aligned with Silicon One’s scalable and flexible architecture.
What they ask for
- Bachelor's or a Master's Degree in Electrical or Computer Engineering.
- At least 7 years of experience.
- Experience coding in Verilog/System Verilog.
- Experience with front-end tools and industry-standard interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories.
Nice to have
- Experience with power optimization, power intent (UPF), or power estimation.
- Experience with DFT/MBIST or post-silicon debug.
Pay
$167,700.00 to $245,200.00 USD base salary; $167,700.00 - $282,000.00 USD base salary; $149,100.00 - $250,900.00 USD base salary
Tools
Verilog, System Verilog, Verilog simulators, linting, CDC checkers, synthesis, formal verification, UPF
Model-written summary · the original posting is authoritative