Drimva

CoreWeave

Senior Firmware Engineer, FPGA

$182K–$242K

New York, NY / Sunnyvale, CA +3 · Senior · Full-time · Posted Jun 22, 2026

Location
New York, NY / Sunnyvale, CA
Bellevue, WA
Manhattan, New York, United States
California, USA
Experience
5+ years of professional experience in firmware, embedded systems, or FPGA development for server-class, platform, or embedded systems.
Education
Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
Visa sponsorship
The position requires access to export-controlled information. Applicants must be a U.S. person, eligible to access the information without export authorization, or eligible and reasonably likely to obtain required authorization; CoreWeave may decline to pursue export licensing.

About the job

Designs and validates FPGA-based platform functionality and integrates it with firmware, BIOS, and hardware for AI compute systems.

What you'll do

  • Develop, integrate, bring up, and validate FPGA logic and platform interfaces across hardware revisions.
  • Debug cross-layer issues and improve reliability, telemetry, fault handling, and automated testing.
  • Collaborate with vendors and internal teams; document designs and contribute technical leadership.

What they ask for

  • Hands-on professional experience developing with Intel/Altera FPGA devices.
  • Strong proficiency in Verilog or SystemVerilog and in C or C++.
  • Experience with board bring-up, hardware validation, and system-level debugging.
  • Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field.

Nice to have

  • Experience integrating FPGA functionality with BMC firmware, BIOS, CPLDs, or platform management interfaces.
  • Experience with server or data-center platforms, lab debug tools, or Python/Bash automation.

Pay

USD $182,000 to $242,000 (base salary)

Tools

Intel/Altera, Quartus, Verilog, SystemVerilog, C, C++, Linux, Git

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 5, 2026 (UTC)