d-Matrix
Sr. Staff Design Verification Engineer
$175K–$265K
Santa Clara · Hybrid · Senior Staff · Full-time · Posted Apr 3, 2025
- Experience
- 12+ years with a BS; 7+ years with an MS.
- Education
- BS in Electrical Engineering, Computer Science, or a related field; MS preferred.
About the job
Develop and lead verification for d-Matrix’s ASIC/SoC designs, from architecture through tape-out and silicon bring-up, supporting its in-memory computing architecture.
What you'll do
- Develop verification plans and build UVM/OVM-based environments; write and debug SystemVerilog testbenches.
- Drive debug, root-cause analysis, and coverage closure to achieve verification sign-off.
- Coordinate verification strategy with design, architecture, and physical design teams, and improve verification methodology and infrastructure.
What they ask for
- BS in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience, or MS with 7+ years.
- Experience across the full SoC/IP verification cycle, from architecture through tape-out and bring-up.
- Hands-on ASIC/SoC design verification test development and debug experience.
- Fluency with SystemVerilog and verification methodologies such as UVM/OVM/VMM.
Nice to have
- Experience with C/C++ and SystemC.
- Track record leading multiple SoC verification environments and tape-out efforts.
Pay
$175K – $265K (base salary)
Tools
SystemVerilog, UVM, OVM, VMM, C/C++, SystemC
AI focus
Verification work for in-memory computing architectures used in AI infrastructure.
Model-written summary · the original posting is authoritative