d-Matrix
Sr. Staff PCB Design Engineer
$175K–$265K
Santa Clara · Hybrid · Senior Staff · Full-time · Posted Aug 28, 2026
- Experience
- 10+ years in high-speed, high-density PCB layout for servers, networking, or AI accelerators.
- Education
- BS in Electrical/Electronic Engineering or equivalent practical experience.
About the job
Leads PCB layout and design methodology for high-complexity AI accelerator cards and system baseboards, including high-speed signal routing and power delivery.
What you'll do
- Lead full-cycle layout for AI accelerator cards and system baseboards, and manage Cadence Allegro constraint hierarchies.
- Automate layout tasks, design audits, DRC checks, and reporting using scripts or Allegro’s API.
- Define stack-ups and partner with power, ASIC, manufacturing, fabricators, and CMs to meet performance and production requirements.
What they ask for
- BS in Electrical/Electronic Engineering or equivalent practical experience.
- Proficiency in Cadence Allegro Constraint Manager and proven ability to automate design work with SKILL scripts or Allegro’s API.
- Deep understanding of high-speed routing and HDI/ELIC design.
- Track record routing 112G SerDes and complex DDR5/HBM interfaces.
Nice to have
- Experience establishing library management and standardized footprint/padstack processes.
- Familiarity with PLM/PDM integration or knowledge of PCB warpage mitigation.
Pay
$175K – $265K (base salary); Offers Equity; Offers Bonus
Tools
Cadence Allegro, SKILL, Python, TCL, PCIe Gen5/6, CXL, Megtron 7/8, DDR5/HBM
AI focus
Designs and lays out PCBs for AI accelerator platforms and their high-speed AI silicon systems.
Model-written summary · the original posting is authoritative