d-Matrix
Sr. Staff Power Performance Architect
$165K–$265K
Santa Clara · Hybrid · Senior Staff · Full-time · Posted Sep 13, 2026
- Experience
- 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design.
- Education
- Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
About the job
Own pre-silicon power estimation for AI accelerators and develop architectural tools and hardware capabilities that balance power and performance.
What you'll do
- Lead RTL- and physical-design-level power estimation, and use findings to optimize designs.
- Build an AI workload power estimation tool using system configuration and die-level metrics.
- Drive performance monitoring and hardware design improvements, and contribute to microarchitecture, RTL, verification, and silicon bring-up.
What they ask for
- Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
- Solid understanding of power, performance, microarchitecture, RTL, physical design, and the full IC design flow.
- Familiarity with at least one EDA tool for power estimation.
- Programming proficiency in TCL and Python.
Nice to have
- Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average.
- Familiarity with power/frequency scaling techniques or power delivery network analysis.
Pay
$165K – $265K (base salary); Offers Equity; Offers Bonus
Tools
TCL, Python, EDA
AI focus
Develop power estimation tools and improve power-performance capabilities for AI accelerator workloads.
Model-written summary · the original posting is authoritative