d-Matrix
Staff Analog Design Engineer, SerDes Clocking
$155K–$250K
Santa Clara · Hybrid · Staff · Full-time · Posted Aug 19, 2026
- Experience
- 5+ years of hands-on analog and mixed-signal circuit design experience.
- Education
- BS/MS/PhD in Electrical Engineering.
About the job
Own transistor-level design and silicon characterization of the SerDes clocking subsystem, including PLL, phase interpolator, clock distribution, and CDR.
What you'll do
- Design and verify PLL, phase interpolator, clock distribution, and CDR blocks, including jitter and phase-noise analysis.
- Develop block verification and modeling, drive layout, and collaborate across teams to close timing, jitter budgets, and calibration.
- Lead silicon bring-up and bench characterization, correlating measured performance with simulation.
What they ask for
- BS/MS/PhD in Electrical Engineering.
- Hands-on analog and mixed-signal circuit design experience.
- Silicon-proven ownership of a low-jitter PLL, phase interpolator, or CDR loop in a high-speed SerDes link.
- Experience with advanced FinFET or GAA process nodes, analog design tools, and silicon bring-up and bench debug.
Nice to have
- Die-to-die interconnect experience, such as UCIe, BoW, or proprietary D2D PHY.
- Experience with forwarded-clock or matched-source-synchronous architectures, digital/hybrid PLL/CDR, or relevant specifications.
Pay
$155K – $250K (base salary)
Tools
MATLAB, Python, Verilog-A, Cadence Virtuoso, Spectre, UCIe, BoW, BERTs
Model-written summary · the original posting is authoritative