Staff Analog Design Engineer, TX/RX Datapath

What you'll do

• Design and verify transmit, receive, and equalization blocks; derive block specifications from link budgets and evaluate architecture trade-offs.
• Build simulation and modeling environments, support layout and system integration, and collaborate with package/signal-integrity and backend engineers.
• Take designs through testboard development, silicon bring-up, and bench characterization, correlating measurements with simulations.

What they ask for

• Demonstrated ownership of a SerDes transmit or receive datapath block through working silicon in a high-speed link.
• Deep knowledge of high-speed driver and receiver-front-end design and equalization, plus practical familiarity with adjacent clocking and CDR blocks.
• Practical command of jitter and noise analysis, including decomposition, budgeting, and simulation methods.
• Experience with advanced FinFET or GAA process nodes, analog design and simulation tools, link/channel modeling, and high-speed lab bring-up and debug.

Nice to have

• Die-to-die interconnect experience, PAM4 or DSP-based receiver architectures, or familiarity with specifications such as UCIe, OIF CEI-112G/224G, IEEE 802.3, and PCIe Gen6/Gen7.
• Experience porting datapath blocks across process nodes, generating IBIS-AMI models, developing SerDes ATE or production tests, or contributing to standards bodies.

Pay

$155K – $250K (base salary)

Tools

Cadence Virtuoso, Spectre, MATLAB, Python, Verilog-A, S-parameter models, UCIe, BERTs