Drimva

Efficient Computer

Digital Verification Engineer

$130K–$180K

San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3 · Full-time · Posted Oct 21, 2026

Location
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Austin, TX
Pittsburgh, PA
San Francisco, California, United States
Experience
4+ years in ASIC/SoC design verification, with multiple projects taken through tapeout.
Education
Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.

About the job

Own functional verification of SoC blocks and subsystems, including proprietary Fabric technology, by developing testbenches, closing coverage, and finding design bugs before silicon.

What you'll do

  • Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests; create verification plans with design and architecture teams.
  • Write assertions and coverage models, drive coverage closure, and debug simulation failures with designers.
  • Contribute to regression automation and dashboards, and support gate-level simulation and sign-off.

What they ask for

  • Hands-on UVM testbench development, including agents, scoreboards, sequences, and constrained-random tests.
  • Experience defining functional coverage and closing code and functional coverage at block or subsystem level; working knowledge of SystemVerilog Assertions.
  • Ability to independently debug simulation failures using waveforms, logs, and design knowledge; proficiency in Python for automation and regression flows.
  • Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.

Nice to have

  • C/C++ experience; exposure to formal verification (JasperGold or similar) or power-aware verification (UPF).
  • Experience building or using AI agentic flows for DV; knowledge of computer architecture or dataflow architectures.

Pay

$130,000 to $180,000 USD base salary

Tools

UVM, SystemVerilog, Python, C/C++, DPI, JasperGold, UPF

AI focus

Preferred experience building or using AI agentic flows for design verification.

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 4, 2026 (UTC)