Efficient Computer
Lead Digital Verification Engineer
$200K–$260K
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3 · Full-time · Posted Feb 18, 2026
- Location
- San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Austin, TX
Pittsburgh, PA
San Francisco, California, United States - Experience
- 10+ years in ASIC/SoC design verification, with at least 3 years in a lead role.
- Education
- Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
About the job
Leads functional verification of complex SoC/IP designs from specification through tapeout, owning verification strategy, team execution, and sign-off readiness.
What you'll do
- Define verification strategy, plans, coverage goals, and sign-off criteria across block, subsystem, and full-chip levels.
- Architect UVM testbenches, drive stimulus and coverage closure, and manage debugging, bug lifecycle, and regression flows.
- Lead and mentor verification engineers; coordinate across hardware teams and represent verification readiness in tapeout decisions.
What they ask for
- Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of progressive ASIC/SoC design verification experience, including at least 3 years in a lead role owning strategy, sign-off, and team execution.
- Deep UVM expertise and advanced SystemVerilog proficiency, including classes, constraints, functional coverage, SVA, interfaces, and packages.
- Track record of coverage closure to tapeout on complex SoC/ASIC designs; strong debugging, SoC architecture, scripting, and communication skills.
Pay
$200,000 to $260,000 USD base salary; 10% annual bonus (amount not stated)
Tools
UVM, SystemVerilog, Python, Perl, Tcl, ARM, RISC-V, AMBA AXI/ACE/CHI
AI focus
The company builds energy-efficient computing hardware for AI; this role verifies SoC/IP designs, including the company's second product line.
Model-written summary · the original posting is authoritative