Efficient Computer
Lead RTL Design Engineer
$200K–$275K
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3 · Full-time · Posted Apr 30, 2026
- Location
- San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Austin, TX
Pittsburgh, PA
San Francisco, California, United States - Experience
- 8+ years of RTL design experience.
About the job
Leads microarchitecture definition and RTL implementation for Efficient Computer’s energy-efficient SoC, from specifications through synthesis and silicon bring-up.
What you'll do
- Own processor and compute-unit microarchitecture, including dataflow pipelines, execution units, interfaces, and performance, power, and area targets.
- Drive interconnect, memory, reconfiguration, power-management, and hardware/software co-design decisions; author specifications and lead design reviews.
- Collaborate on verification, PPA optimization, mentoring, and silicon bring-up.
What they ask for
- 8+ years of RTL design experience, including tape-out ownership of a dataflow design, on-chip network, memory subsystem, or peripheral integration on a processor or accelerator SoC.
- Deep SystemVerilog RTL proficiency and hands-on experience with on-chip memory design and low-power RTL techniques.
- Understanding of parallel execution models and RTL-level familiarity with at least one on-chip bus protocol.
- Experience taking RTL through synthesis and timing closure; experience with memory compiler toolchains.
Nice to have
- RTL ownership of a dataflow engine, NPU, or streaming DSP; compiler or graph-optimization collaboration.
- Experience with NVM controller RTL, functional safety, AI graph formats, formal verification, or edge-AI/IoT/wearable SoC tape-outs.
Pay
$200,000 to $275,000 USD base salary
Tools
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC
AI focus
The role designs energy-efficient compute hardware for AI and other workloads, including dataflow execution and hardware/software co-design with compiler teams.
Model-written summary · the original posting is authoritative