Drimva

Efficient Computer

Physical Design Engineer - Timing Lead

$180K–$260K

San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX OR Remote +4 · Remote · Full-time · Posted Feb 20, 2026

Location
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX OR Remote
Austin, TX
Pittsburgh, PA
Remote, United States
San Jose, CA
Experience
5+ years with a Master's degree, or 3+ years with a PhD.
Education
Master's or PhD in Electrical Engineering.

About the job

Leads timing methodology and convergence for IP, subsystem, and SoC designs, supporting sign-off and product development for Efficient Computer’s low-power processor.

What you'll do

  • Develop timing flows and methodology for advanced FinFET and multi-patterning technologies; own timing convergence and sign-off for IP, subsystem, and SoC blocks.
  • Define timing margins, corners, extraction methodology, and checks; drive SDC constraints with RTL, DFT, and IP teams.
  • Improve timing-flow consistency and efficiency, coordinate third-party timing work, and support pre-silicon to post-silicon timing correlation.

What they ask for

  • Master's degree in Electrical Engineering and 5+ years of industry experience, or PhD in Electrical Engineering and 3+ years of industry experience.
  • Delivered IP/SS or SoC STA sign-off for multiple tape-outs at 12nm or below.
  • Experience with EDA flows using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice), including hierarchical design and abstraction techniques.
  • Hands-on timing convergence experience in high-frequency, low-power designs; expert static timing analysis, constraints, corners, voltage definitions, and timing margining; strong TCL, shell, and Python scripting.

Nice to have

  • Knowledge of computer architecture, physical design, or ASIC implementation.
  • Experience with full-chip sign-off budgeting, CAD flow infrastructure, or analog/mixed-signal macro integration.

Pay

$180,000 to $260,000 USD base salary

Tools

Cadence Tempus, Synopsys Primetime, Cadence, Synopsys, Mentor, PT/Hspice, TCL, python

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 4, 2026 (UTC)