Efficient Computer
Senior Digital Verification Engineer - Contract
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3 · Senior · Full-time · Posted Oct 14, 2026
- Location
- San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Austin, TX
Pittsburgh, PA
San Francisco, California, United States - Experience
- 8+ years of ASIC/SoC design verification, with multiple projects taken from testbench development through tapeout.
- Education
- Bachelor's or Master's/PhD in Electrical Engineering, Computer Engineering, or a related field.
About the job
Own verification of complex SoC blocks and subsystems, from specification review and testbench development through coverage sign-off and handoff.
What you'll do
- Create verification plans and architect or extend UVM/SystemVerilog testbenches, including agents, scoreboards, reference models, sequences, and constrained-random tests.
- Write assertions and functional coverage models, debug simulation failures with RTL designers, and drive coverage to sign-off.
- Report status, risks, and coverage gaps, and document verification environments for handoff.
What they ask for
- Expertise in UVM testbench architecture and SystemVerilog verification, including classes, constraints, interfaces, functional coverage, and SVA.
- Track record driving functional and code coverage to sign-off on multi-million-gate designs.
- Strong independent simulation-debug skills using industry-standard tools; Python for regression automation, log analysis, and coverage processing.
- Ability to ramp quickly and deliver with minimal supervision; clear written and verbal communication.
Nice to have
- C/C++ for reference modeling or SoC-level tests, including DPI integration; formal verification with JasperGold or similar.
- Experience with agentic AI flows for DV, computer architecture/dataflow/spatial architectures/ML accelerators, or power-aware verification with UPF.
Pay
USD $80–$130 per hour (1099 contract basis; hourly rate)
Tools
UVM, SystemVerilog, SVA, VCS/Verdi, Xcelium, Questa, Python, JasperGold
AI focus
May build or use agentic AI flows for design verification, such as automated regression triage or failure debugging; this is a preferred qualification.
Model-written summary · the original posting is authoritative