Efficient Computer
Senior RTL Design Engineer
$180K–$245K
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3 · Senior · Full-time · Posted Oct 14, 2026
- Location
- San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Austin, TX
Pittsburgh, PA
San Francisco, California, United States - Experience
- 8-10 years; significant contributions to at least two tapeout cycles.
About the job
Design, integrate, and sign off synthesis-ready RTL for blocks in an ultra-low-power SoC, from microarchitecture through tapeout and silicon bring-up.
What you'll do
- Implement and integrate RTL for compute fabric, interconnect, memory interfaces, and peripheral subsystems; document designs and present them in reviews.
- Own front-end sign-off, including lint, CDC/RDC, LEC, synthesis, SDC constraints, STA, and timing, area, and power iteration.
- Implement low-power features and support verification, gate-level debug, and silicon bring-up.
What they ask for
- 8-10 years of front-end digital design experience on processor, accelerator, or SoC products, with significant contributions to at least two tapeout cycles.
- Strong proficiency in synthesizable SystemVerilog and hands-on experience with lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA.
- Experience with UPF-driven low-power design techniques and at least one on-chip bus protocol at RTL level.
- Experience with on-chip memories and RTL simulation/debug; clear written and verbal communication.
Nice to have
- Experience with on-chip networks, dataflow pipelines, or memory subsystems; familiarity with NVM controller RTL.
- Experience with RTL/gate-level power analysis, DFT, or scripting in Python, Tcl, or Perl.
Pay
$180,000 to $245,000 USD base salary; 10% annual bonus (amount not specified)
Tools
SystemVerilog, UPF, AXI, AHB, APB, TileLink, Python, Tcl
AI focus
Design hardware for an energy-efficient computing architecture that supports AI; the role focuses on SoC RTL design rather than AI model development.
Model-written summary · the original posting is authoritative