Efficient Computer
Sr Staff Physical Design - SOC Top Lead
$180K–$260K
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3 · Senior Staff · Full-time · Posted Aug 3, 2026
- Location
- San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Austin, TX
Pittsburgh, PA
San Francisco, California, United States - Experience
- Master's route: 5+ years of industry experience; PhD route: 3+ years. Also asks for 8–12+ years of physical design experience and at least 2–3 full chip-top/SoC integration tapeouts.
- Education
- Master's degree in Electrical Engineering or PhD in Electrical Engineering.
About the job
Own top-level SoC physical design from block integration through sign-off and tapeout-ready GDS, while coordinating cross-functional convergence and setting chip-top methodology.
What you'll do
- Drive full-chip integration, timing closure, power planning, physical verification, signal-integrity closure, and tapeout readiness.
- Coordinate DFT, package/IO, architecture, and block-level teams on convergence tradeoffs, schedules, and sign-off.
- Mentor block-level physical design engineers and establish chip-top closure methodology and flow standards.
What they ask for
- Master's degree in Electrical Engineering with 5+ years of industry experience, or PhD in Electrical Engineering with 3+ years of industry experience.
- 8–12+ years of physical design experience, including at least 2–3 full chip-top/SoC integration tapeouts.
- Hands-on experience with advanced nodes; proven full-chip timing closure across multiple corners/modes; and strong PDN/IR-drop/EM analysis experience.
- Chip-level DFT integration experience; tool fluency in Innovus (or ICC2), Tempus/PrimeTime, RedHawk, and Calibre; excellent TCL, shell, and python scripting skills.
Nice to have
- Familiarity with package co-design, including flip-chip/BGA, C4 bumps, and ball maps.
- Experience with non-standard/novel architectures or integrating analog/mixed-signal macros at top level.
Pay
$180,000 to $260,000 USD base salary; 10% annual bonus (no amount stated)
Tools
Innovus, ICC2, Tempus, PrimeTime, RedHawk, Calibre, TCL, python
AI focus
Design physical implementation for next-generation SoCs supporting energy-efficient general-purpose computation, including AI.
Model-written summary · the original posting is authoritative