Efficient Computer
Staff Digital Verification Engineer
$160K–$245K
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3 · Staff · Full-time · Posted Sep 1, 2026
- Location
- San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Austin, TX
Pittsburgh, PA
San Francisco, California, United States - Experience
- 10+ years of progressive ASIC/SoC design verification experience, including multiple full cycles of ownership from testbench architecture through tapeout.
- Education
- Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
About the job
Drive functional verification of complex SoC/IP designs from specification through tapeout, helping develop verification processes as products move toward release and volume production.
What you'll do
- Own verification across design cycles, from testbench architecture through tapeout.
- Drive functional and code coverage to tapeout sign-off and debug complex simulation failures.
- Develop test automation, log analysis, coverage post-processing, and regression flows.
What they ask for
- Expertise in UVM-based testbench architecture and constrained-random verification methodology.
- C/C++ experience for modelling or verification.
- Demonstrated coverage sign-off on complex, multi-million-gate SoC/ASIC designs and ability to debug complex simulation failures.
- Proficiency in Python for verification automation and regression development.
Nice to have
- Formal verification experience (JasperGold or similar).
- Experience building or using AI Agentic flows for DV.
Pay
$160,000 to $245,000 USD base salary
Tools
UVM, SystemVerilog, C/C++, Python, JasperGold, ARM, RISC-V, AMBA AXI/ACE/CHI
AI focus
Experience building or using AI Agentic flows for design verification is a preferred qualification.
Model-written summary · the original posting is authoritative