Elevate Semiconductor
Staff Analog IC Layout Engineer (Block & Chip)
$145K–$175K
San Diego, California · Staff · Full-time · Posted Sep 3, 2026
- Experience
- Minimum of 8 years of professional experience in analog and mixed-signal IC layout design.
- Education
- Bachelor’s degree in Electrical Engineering or a related field.
About the job
Owns block- and chip-level physical layout and verification of analog and mixed-signal ICs for the ATE market, helping drive designs through tapeout.
What you'll do
- Perform analog and mixed-signal IC layout, develop floorplans, and optimize component placement.
- Run LVS and DRC verification and resolve layout, verification, and manufacturability issues.
- Collaborate with analog, digital, packaging, and other teams to meet circuit and chip-performance goals.
What they ask for
- Bachelor’s degree in Electrical Engineering or a related field.
- Minimum of 8 years of professional experience in analog and mixed-signal IC layout design.
- Strong understanding of analog CMOS circuits and device physics, and knowledge of the IC design, qualification, and manufacturing lifecycle.
- Hands-on experience with industry-standard EDA tools such as Cadence, Mentor Graphics, or Tanner; proficiency in LVS and DRC verification using Cadence or Mentor tools.
Nice to have
- Experience with high-voltage (100V+) BCD, LDMOS, and STI layout; mixed-voltage, high-speed, precision analog, data converter, or BiCMOS layout.
- Programming and scripting experience, particularly with SKILL and Calibre scripts.
Pay
$145,000.00 to $175,000.00 USD base salary
Tools
Cadence, Mentor Graphics, Tanner, LVS, DRC, BCD, LDMOS, SKILL
Model-written summary · the original posting is authoritative