Eliyan
Digital - ASIC Design Automation & Integration Engineer
Bay Area, Vancouver or Toronto · On-site · Full-time · Posted May 13, 2026
- Experience
- 5+ years in ASIC or SoC design or design automation.
- Education
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Visa sponsorship
- Authorization to work in the United States or Canada is required; visa sponsorship may be considered for exceptional candidates.
About the job
Own design-quality signoff and automation for ASIC programs, including lint, CDC, synthesis, RTL integration, CI/CD, and AI-augmented violation review tooling.
What you'll do
- Define lint, CDC, and synthesis signoff criteria; manage waivers and analyze synthesis regressions.
- Integrate digital IP into PHY and chip-level hierarchies, automate integration checks, and manage IP release packaging.
- Own RTL quality CI/CD pipelines, dashboards, and LLM-based violation triage and documentation tools.
What they ask for
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 5+ years in ASIC or SoC design or design automation, with hands-on experience running and analyzing lint, CDC, or synthesis tools.
- Familiarity with lint/CDC/RDC tools and synthesis tools; working knowledge of SystemVerilog and RTL front-end flows.
- Proficiency in Python, Tcl, shell scripting, Git, Linux, and Makefiles; experience maintaining CI/CD pipelines.
Nice to have
- Experience with waiver management systems, violation databases, or design quality dashboards.
- Experience with register map automation, IP packaging standards, UPF, Static Timing Analysis, LLM APIs or agent frameworks, or digital IP integration and release.
Tools
SystemVerilog, Python, Tcl, Git, Linux, Makefiles, Jenkins, PeakRDL
AI focus
Develop LLM-based lint and CDC violation triage, automated annotated pull requests, spec-to-RTL consistency checks, and CI-integrated documentation generation; benchmark output quality and false-negative rates.
Model-written summary · the original posting is authoritative