Drimva

Eliyan

Digital - Principal Systems/DSP Engineer

Bay Area · On-site · Principal · Full-time · Posted Dec 22, 2025

Experience
10+ years; hands-on work at 112G PAM4 or higher data rates.
Education
Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or related fields.

About the job

Defines DSP architecture and algorithms for high-speed SerDes, from system modeling and link design through silicon bring-up and characterization.

What you'll do

  • Architect low-power DSP for 224G PAM4 and 448G SerDes, including equalization, adaptive algorithms, and CDR.
  • Build behavioral models and run system-level simulations to set performance targets and analyze power, BER, and link budgets.
  • Lead cross-functional implementation, silicon validation, and technical guidance for customers and partners.

What they ask for

  • 10+ years in DSP system architecture and algorithm development for high-speed serial communications, including hands-on work at 112G PAM4 or higher.
  • Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
  • Expertise in digital communications and signal processing, including PAM4, equalization, CDR, and statistical channel modeling.
  • Hands-on 112G/224G SerDes product experience with tapeout or silicon characterization results.

Nice to have

  • Experience with chiplet D2D interconnects, VCSEL/EML interfaces, or DRAM/HBM PHY systems.

Tools

MATLAB, Simulink, C, Python, Ethernet (IEEE 802.3ck/df/dj), PCIe, UCIe, OIF CEI

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 5, 2026 (UTC)