Eliyan
Digital - SerDes Digital Design Lead
Bay Area · On-site · Full-time · Posted Feb 20, 2026
- Experience
- 12+ years; requires proven tapeout experience at 112G PAM4 or higher data rates.
- Education
- Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related fields.
About the job
Leads architecture and RTL implementation of high-speed SerDes digital IP for 224G and 448G chiplet interconnects, from design through tapeout and post-silicon debug.
What you'll do
- Lead design of SerDes TX/RX datapaths, CDR, equalization, FEC, and PHY control logic.
- Drive RTL quality, optimization, AMS integration, and coordination with verification, DFT, physical design, and backend teams.
- Own design milestones through tapeout, support post-silicon characterization, and contribute to standards and link bring-up.
What they ask for
- 12+ years of digital design experience in high-speed SerDes, PHY, or transceiver IP, with tapeout experience at 112G PAM4 or higher.
- Strong SystemVerilog RTL skills and understanding of synthesis, timing closure, CDC/RDC, and DFT.
- Expertise in SerDes DSP architectures, including FFE, DFE, MLSE, CTLE digital controls, CDR, and PAM4 adaptation/calibration.
- Working knowledge of IEEE 802.3, OIF CEI, FEC architectures, and/or UCIe; experience with advanced process nodes and digital-analog integration.
Nice to have
- Experience with VCSEL or EML interconnects, chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces.
Tools
SystemVerilog, IEEE 802.3, OIF CEI, UCIe, RS-FEC KP4/KP8, 5nm, 3nm, FinFET/GAA
AI focus
Develops power-efficient SerDes interconnects for data center and AI/ML applications.
Model-written summary · the original posting is authoritative