Eliyan
Digital - Staff Digital Design Engineer - PHY
Bay Area, Vancouver or Toronto · On-site · Staff · Full-time · Posted Dec 23, 2025
- Experience
- 8+ years digital frontend design, including 4+ years in PHY or high-speed interfaces; 3+ successful tapeouts as design lead. Preferred: 12+ years with demonstrated technical leadership.
About the job
Leads the digital frontend design of Eliyan’s D2D PHY, from microarchitecture and RTL through synthesis and physical-design handoff.
What you'll do
- Define PHY architecture and design RTL for link training, calibration, rate adaptation, clock-domain crossing, FIFO alignment, and lane deskew.
- Optimize synthesis and deliver constraints, power specifications, and netlists for physical-design handoff.
- Coordinate with analog, verification, physical-design, and firmware teams; mentor designers and lead technical reviews.
What they ask for
- 8+ years in digital frontend design, including 4+ years in PHY or high-speed interfaces.
- 3+ successful tapeouts as design lead in advanced nodes (7nm or below).
- Deep expertise in D2D PHY, DDR PHY, or SerDes digital design; expert SystemVerilog RTL and synthesis optimization skills.
- Experience with high-speed interfaces, CDC, link training, elastic buffers, synthesis tools, SDC, UPF, and STA methodology; ability to lead and coordinate across teams.
Nice to have
- UCIe PHY design or certification; DDR4/DDR5/LPDDR PHY or DFI; SerDes digital control, PCIe PHY, or CXL PHY experience.
- 12+ years with technical leadership; advanced packaging, PHY firmware, Python/Perl/Tcl scripting, or PHY publications/patents.
Tools
UCIe, SystemVerilog, Synopsys DC/Fusion Compiler, Cadence Genus, SDC, UPF, Python/Perl/Tcl
AI focus
The PHY work enables chiplet-based AI and HPC systems; no AI development duties are stated.
Model-written summary · the original posting is authoritative