Eliyan
DV - Digital Verification Engineer (Senior levels - Staff +)
Vancouver, BC OR Bay Area, CA · On-site · Staff · Full-time · Posted Mar 5, 2025
- Experience
- 6+ years overall; 3+ years working on specified Ethernet standards clauses.
- Education
- Master’s or Ph.D. in Electrical Engineering or related fields.
About the job
Develops and leads digital verification for connectivity IP and chiplets, including PHYs and controllers, from test planning through regression and RTL freeze.
What you'll do
- Develop verification plans, SystemVerilog/UVM environments, and block- and chip-level test cases; maintain regressions for CI/CD.
- Review microarchitecture, test plans, and coverage with design teams; ensure IP compliance with IEEE 802.3 and integrate third-party VIPs.
- Maintain DPI-based firmware simulation and GLS environments, track verification progress, and provide technical leadership to junior engineers.
What they ask for
- Master’s or Ph.D. in Electrical Engineering or a related field.
- 6+ years of experience; 3+ years working on Ethernet 802.3 standards clauses related to 100G, 200G, 400G, 800G, Auto-Negotiation, and Link Training.
- Hands-on verification experience with serial transmission protocols and products.
- Strong expertise in UVM, SystemVerilog test environments and assertion coding; proficiency with regression management and coverage-analysis tools.
Nice to have
- Knowledge of DRAM controllers/PHYs and HBM memory.
- Experience verifying third-party mixed-signal IP and integrating VIPs.
Tools
SystemVerilog, UVM, DPI, GLS, Ethernet, IEEE 802.3, DRAM, HBM
Model-written summary · the original posting is authoritative