Eliyan
DV - Director of Design Verification
Bay Area · On-site · Director · Full-time · Posted Feb 16, 2026
- Experience
- 15+ years; at least 5 years in a people-management or leadership role.
- Education
- Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or related fields.
About the job
Leads and scales the design verification team and owns verification strategy, execution, and tapeout readiness across PHY and controller products.
What you'll do
- Define verification methods and drive verification planning and execution across product lines and subsystems.
- Build and manage the verification team, partnering with cross-functional teams and reporting program status to executives.
- Improve verification infrastructure and oversee AMS, firmware co-simulation, and gate-level simulation flows.
What they ask for
- Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years in design verification of high-speed serial interfaces, PHYs, and controller IPs, including at least 5 years in a people-management or leadership role.
- Expertise in SystemVerilog/UVM, constrained-random, assertion-based, and formal verification.
- Experience with AMS verification, including RNM, Verilog-AMS, SVAMS co-simulation, and mixed-signal behavioral modeling.
Nice to have
- Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect verification.
Tools
SystemVerilog/UVM, RNM, Verilog-AMS, SVAMS, DPI, CI/CD, IEEE 802.3, UCIe
AI focus
Drive verification innovation, including AI/ML-assisted verification.
Model-written summary · the original posting is authoritative