Eliyan
DV - Staff (+) Verification Engineer - AMS modeling
Bay Area, Vancouver or Toronto · On-site · Staff · Full-time · Posted May 20, 2026
- Experience
- 5+ years of relevant experience.
- Education
- BS in EE or related field.
About the job
Lead verification of SerDes and develop and verify RNM AMS SystemVerilog models for PHYs, working with analog and design teams.
What you'll do
- Develop and execute RNM AMS models and ensure they reflect schematics.
- Write and debug SystemVerilog/UVM-compliant test cases.
- Collaborate with design teams to support design quality and verify mixed-signal IP.
What they ask for
- Deep analog design expertise.
- Knowledge of SystemVerilog, test environments, and assertion coding.
- Experience verifying mixed-signal IPs.
Nice to have
- Formal verification experience with Jasper Gold or vc-formal.
- Python/Perl/Tcl scripting for design verification.
Tools
RNM, AMS, SystemVerilog, UVM, Jasper Gold, vc-formal, Python, Perl
Model-written summary · the original posting is authoritative