Eliyan
DV - Staff Verification Engineer - Serdes
Bay Area, Vancouver or Toronto · On-site · Staff · Full-time · Posted Apr 8, 2026
- Experience
- 7 years of verification experience, including 4+ years in PHY or high-speed interfaces; preferred: 10+ years with demonstrated verification technical leadership.
- Education
- BS
About the job
Leads verification of SerDes and other PHYs, developing UVM/SystemVerilog testbenches and test plans for block- and chip-level designs.
What you'll do
- Develop and execute verification plans and test cases for SerDes, PHYs, DSP blocks, TX/RX equalization, and CDR; maintain regression environments.
- Define PHY verification architecture, integrate third-party VIPs, and perform GLS simulation for functional verification and power calculations.
- Collaborate with design teams, track verification progress, and mentor junior verification engineers.
What they ask for
- BS and 7 years of verification experience, including 4+ years in PHY or high-speed interfaces.
- Deep verification expertise in SerDes/PCIePHY, TX/RX equalization, and CDR.
- Strong expertise in UVM/SystemVerilog, test environments, and assertion coding.
- Experience verifying mixed-signal IPs and integrating VIPs.
Nice to have
- 10+ years with demonstrated verification technical leadership.
- Experience with formal verification, GLS simulations, Python/Perl/Tcl scripting, or third-party regression management and coverage analysis tools.
Tools
SystemVerilog, UVM, Jasper Gold, vc-formal, Python, Perl, Tcl
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