Eliyan
PD - IP Lead – Sr Staff, Physical Design
Bay Area · On-site · Senior Staff · Full-time · Posted Feb 9, 2026
About the job
Leads physical design strategy and end-to-end implementation and signoff of ASIC IP, from RTL handoff through GDSII, optimizing quality, schedule, and manufacturability.
What you'll do
- Set IP and partition physical-design strategy and drive implementation, integration, timing closure, and tapeout milestones.
- Develop and improve design flows; lead signoff across timing, power integrity, signal integrity, and physical verification.
- Coordinate with cross-functional teams and report progress, risks, and mitigation to leadership.
What they ask for
- Expertise in physical design, timing closure, and signoff for ASIC IP blocks, including mixed-signal integration and subsystem closure ownership.
- Hands-on experience with floorplanning, power planning, placement, CTS, routing, EM IR, STA, and PV signoff across MMMC scenarios.
- Ability to improve flows through automation and scripting, with strong debugging and data-driven optimization skills.
- Cross-functional leadership and communication skills.
Tools
ASIC, RTL, GDSII, PNR, STA, EM IR, CTS, DRC
Model-written summary · the original posting is authoritative