Eliyan
PD - Principal, Physical Design
Bay Area · On-site · Principal · Full-time · Posted Feb 9, 2026
- Experience
- 8 to 12 years of ASIC physical design experience.
About the job
Leads ASIC physical design from RTL to GDSII, optimizing design flows and delivering complex SoCs through signoff and tapeout.
What you'll do
- Own floorplanning, integration, clocking, and power planning to meet architecture, package, and system constraints.
- Define and improve CTS, routing, and power-grid methodologies; plan hierarchy boundaries, interfaces, and connectivity.
- Lead EM/IR analysis and address hotspots while ensuring timing, physical verification, and signoff readiness.
What they ask for
- 8 to 12 years of ASIC physical design experience owning floorplanning, integration, clocking, and power planning through signoff and tapeout on complex SoCs.
- Expertise in architecture- and package-driven hierarchy planning, boundaries, pin strategy, feedthroughs, repeaters, bus planning, and CTS methodologies.
- Strong EM/IR, PV, and STA awareness, including MMMC, library-corner skew-group balancing, and functional ECO execution.
- Advanced-node exposure to TSMC 3nm, 2nm, or Samsung 2nm.
Tools
RTL, GDSII, synthesis, place-and-route (PnR), static timing analysis (STA), EM/IR, physical verification (PV), MMMC
Model-written summary · the original posting is authoritative