Eliyan
PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |
Bay Area · On-site · Senior Staff · Full-time · Posted May 11, 2026
- Experience
- 15+ years
About the job
Architects and deploys multi-foundry RTL-to-GDSII flows and SoC design methodology, including low-power implementation, hierarchical planning, clocking, and tapeout infrastructure.
What you'll do
- Architect and maintain RTL-to-GDSII flows and validation platforms across foundry nodes and EDA vendors.
- Lead low-power, hierarchical SoC implementation methodology, including power integrity, floorplanning, clocking, synthesis, and timing analysis.
- Drive CAD infrastructure improvements through automation, ML-assisted optimization, and emerging EDA capabilities.
What they ask for
- 15+ years in ASIC CAD, design methodology, or physical design, with a record of leading multi-node, multi-foundry platform deployments.
- Demonstrated deployment of RTL-to-GDSII platforms across external foundry nodes.
- Deep expertise in low-power methodology, including UPF/CPF, multi-voltage integration, retention, and power-domain verification.
- Proven expertise in clocking methodologies and custom cell integration.
Nice to have
- Familiarity with chiplet and 2.5D integration methodology, including die-to-die timing, UCIe/BoW PHY integration, and hierarchical assembly.
- Exceptional problem-solving and communication skills, including presenting to executive leadership and engaging with foundry teams.
Tools
RTL-to-GDSII, Synopsys, Cadence, Siemens, CPF/UPF, EM/IR, SDC, UCIe/BoW
AI focus
Drive CAD infrastructure improvements through automation and ML-assisted optimization.
Model-written summary · the original posting is authoritative