Eliyan
PD - Sr Staff - Physical Verification Lead | Signoff & DRC
Bay Area · On-site · Senior Staff · Full-time · Posted May 11, 2026
- Experience
- 15+ years
About the job
Leads top-level physical verification signoff and bump/package design-rule closure for advanced-node SoCs and chiplet products through tapeout.
What you'll do
- Own hierarchical DRC, LVS, ERC, and DFM signoff; resolve violations and manage foundry waivers.
- Lead bump planning and package co-design checks for flip-chip and 2.5D/3D chiplet assemblies.
- Build PV automation and report signoff readiness to leadership and foundry partners.
What they ask for
- 15+ years of ASIC physical verification experience, with a record of leading advanced-node tapeouts.
- Expertise across at least two of Intel Foundry, TSMC, Samsung, and GlobalFoundries; multi-node experience spanning 28nm through 2nm.
- Expertise in bump planning and package-level DRC for flip-chip and named advanced-packaging technologies.
- Experience with advanced packaging co-design flows and DRC regression infrastructure.
Tools
Calibre, IC Validator, Python, Perl, Tcl, SVRF/TVF, GDSII
Model-written summary · the original posting is authoritative