Etched
Design Verification Engineer - Interface IP
$150K–$350K
Austin · On-site · Full-time · Posted Apr 16, 2026
- Experience
- 5+ years of design verification experience.
About the job
Own verification of interface IP subsystems and ensure their correctness, performance, and compliance within the broader chip architecture and hardware-software stack.
What you'll do
- Own one or more IP subsystems, including PCIe, Ethernet, CPU, low-power peripherals, or sensors; understand vendor configurations and coordinate with internal IP teams.
- Develop and maintain UVM/SystemVerilog verification environments and collaborate with integration and SoC DV teams.
- Drive coverage closure and sign-off by defining metrics, analyzing gaps, and verifying corner cases and stress scenarios.
What they ask for
- 5+ years of design verification experience.
- Hands-on experience with SystemVerilog/UVM and scalable, reusable testbenches.
- Familiarity with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
Nice to have
- Experience handling vendors and integrating IP/VIP’s.
Pay
$150K – $350K USD base salary
Tools
UVM, SystemVerilog, PCIe, Ethernet, AXI/AMBA, ARM/ARC CPUs
Model-written summary · the original posting is authoritative