Etched
Design Verification Engineer - Internal IP
$150K–$350K
Austin · On-site · Full-time · Posted Apr 16, 2026
About the job
Verify custom chip IP—including compute arrays, DMA engines, NoCs, and memory subsystems—for correctness, performance, and silicon readiness across the hardware-software stack.
What you'll do
- Develop and maintain UVM/SystemVerilog testbenches and verification plans for functional correctness, corner cases, concurrency, and performance.
- Debug RTL and testbench issues and collaborate with architects and designers to validate functionality and design intent.
- Partner with SW, FW, and emulation teams on end-to-end bring-up and improve reusable verification infrastructure and coverage.
What they ask for
- Proficiency with UVM and SystemVerilog.
- Strong debugging and problem-solving skills for complex digital designs.
- Solid knowledge of computer architecture and digital design fundamentals.
- Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
Nice to have
- Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques; experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
- Scripting skills (Python/Perl/TCL or similar) for automation, debug, and regression flows.
Pay
$150K – $350K USD base salary
Tools
UVM, SystemVerilog, SystemVerilog Assertions (SVA), Python, Perl, TCL, NoC, AXI
AI focus
Verification work on custom chip IP for inference-focused AI hardware.
Model-written summary · the original posting is authoritative