Etched
Design Verification Engineer - Internal IP
$150K–$350K
San Jose · On-site · Full-time · Posted Jun 11, 2025
About the job
Verify custom chip IP—including compute arrays, DMA engines, and NoCs—for functional correctness, performance, and silicon readiness across hardware and software environments.
What you'll do
- Develop and maintain UVM/SystemVerilog testbenches and verification plans for custom IP.
- Debug RTL and testbench issues, including datapath, protocol, concurrency, and performance problems.
- Collaborate with architecture, design, software, firmware, and emulation teams on validation and bring-up.
What they ask for
- Proficiency with UVM and SystemVerilog.
- Strong debugging and problem-solving skills for complex digital designs.
- Solid knowledge of computer architecture and digital design fundamentals.
- Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
Nice to have
- Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques; experience with systolic arrays, DMA engines, or NoC/AXI protocols.
- Scripting skills (Python/Perl/TCL or similar) for automation, debug, and regression flows.
Pay
$150K – $350K USD base salary
Tools
UVM, SystemVerilog, SystemVerilog Assertions (SVA), Python, Perl, TCL, NoC, AXI
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