Etched
DFT (Design For Test) Engineer
$150K–$350K
San Jose · On-site · Full-time · Posted Feb 28, 2026
- Experience
- 10+ years of DFT engineering experience.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master’s preferred.
About the job
Develops and validates DFT architectures and test processes for ASIC and SoC designs, supporting silicon debug and production quality.
What you'll do
- Develop DFT architectures, integrate test methodologies, and create verification plans for ASIC and SoC designs.
- Analyze test results and silicon debug data; support post-silicon bring-up, failure analysis, and improvements to coverage, yield, and reliability.
- Partner with design, test, manufacturing, and quality teams to optimize production testing and maintain DFT documentation.
What they ask for
- 10+ years of DFT engineering experience, including successful ASIC or SoC test implementations.
- Understanding of digital design, verification methodologies, and DFT implementation practices.
- Proficiency in System Verilog and industry-standard EDA tools.
- Scripting and automation experience using Python, Perl, or TCL.
Nice to have
- Master’s degree; mixed-signal DFT, IEEE 1149.1 (JTAG), or IEEE 1500 experience.
- Yield analysis, product engineering, or test cost reduction and quality improvement experience.
Pay
$150K – $350K (base salary)
Tools
System Verilog, Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent, Python, Perl, TCL
AI focus
The company builds inference-focused frontier AI hardware; the role focuses on DFT and test engineering, not AI development.
Model-written summary · the original posting is authoritative