Etched
DFT Intern
San Jose · On-site · Internship · Posted Apr 13, 2026
- Experience
- No prior DFT experience is necessarily required.
- Education
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
About the job
Supports DFT flow automation and chip-level regression on Caelius, including DFT verification and ATPG flow development.
What you'll do
- Review and refine DFT flow automation for chip-level regression on Caelius.
- Contribute to DFT verification, including MBIST, Scan, BSCAN, and SSN simulations.
- Develop flows for various ATPG fault models.
What they ask for
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with a hardware description language (Verilog or SystemVerilog).
- Exposure to ASIC or SoC design concepts and digital logic design fundamentals.
- Familiarity with standard ASIC design flow steps and scripting in Python, Tcl, or another language.
Nice to have
- Knowledge of DFT concepts, Tessent or similar DFT tooling, and ATPG fault models.
- Exposure to DFT flow automation or regression infrastructure; familiarity with clocking and reset schemes.
Tools
Caelius, Verilog, SystemVerilog, Python, Tcl, Tessent
AI focus
Learn quickly about transformers and other aspects of modern artificial intelligence.
Model-written summary · the original posting is authoritative