Etched
Formal Verification - DV
San Jose · On-site · Full-time · Posted Jun 10, 2026
- Experience
- 5+ years of design verification experience; significant hands-on formal verification experience on complex digital designs or shipping silicon.
About the job
Drives formal verification of custom IP, interfaces, and SoC subsystems in ASICs to prove design correctness, find corner-case bugs, and improve verification closure.
What you'll do
- Define formal verification strategy and plans, and build reusable verification environments and properties.
- Drive proof convergence and formal sign-off using abstractions, coverage metrics, and related methods.
- Debug design issues and coordinate verification across architecture, RTL, DV, emulation, software, and firmware teams.
What they ask for
- 5+ years of design verification experience, including significant hands-on formal verification on complex digital designs or shipping silicon.
- Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
- Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
- Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
Nice to have
- Experience verifying systolic arrays, DMA engines, NoCs, memory subsystems, arithmetic datapaths, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers.
- Scripting experience with Python, TCL, Perl, or similar.
Pay
$500 per month credit for waiving medical benefits; $2.5k per month housing subsidy for those living within walking distance of the office
Tools
SystemVerilog, SystemVerilog Assertions, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, Python, TCL, Perl
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