Etched
Physical Design Engineer - Block Level, Subsystem Implementation
$200K–$375K
San Jose · On-site · Full-time · Posted Jul 23, 2026
- Experience
- 5–10+ years of previous experience with PD.
About the job
Own block-level and subsystem physical design from synthesis through GDSII sign-off, optimizing PPA and collaborating with RTL designers to support hierarchical integration.
What you'll do
- Lead physical design, timing closure, and sign-off, including floorplanning, synthesis, placement, CTS, routing, and physical verification.
- Generate integration views and timing budgets; provide RTL feedback and improve owned blocks and shared flows.
- Oversee outsourced physical design work and ensure delivered blocks meet quality and closure requirements.
What they ask for
- Experience with physical design tools, flows, and methodology from RTL synthesis to GDSII sign-off.
- Back-end design and timing-closure experience on advanced process nodes (5nm and below).
- Experience with automated RTL-to-GDSII flows using Cadence (Innovus, Genus) or Synopsys (Fusion Compiler), and sign-off tools such as PrimeTime, Tempus, or Voltus.
- Experience with listed low-power, verification, implementation, analysis, and scripting methods, including UPF, Tcl, Python, or Perl.
Nice to have
- Familiarity with modern ML and LLM architectures or AI tools for programming.
- Startup experience or comfort in fast-paced environments.
Pay
$200K – $375K USD base salary
Tools
Cadence, Innovus, Genus, Synopsys, Fusion Compiler, PrimeTime, Tempus, Voltus
AI focus
The role implements physical design for inference-focused AI hardware; familiarity with modern ML and LLM architectures and AI coding tools is preferred.
Model-written summary · the original posting is authoritative