Etched
Physical Design Engineer - Block Level, Subsystem Implementation
$200K–$375K
Austin · On-site · Full-time · Posted Jul 30, 2026
- Experience
- 5-10+ years of previous experience with PD.
About the job
Own block-level and subsystem physical design from synthesis through GDSII sign-off, optimizing PPA and collaborating with RTL designers.
What you'll do
- Execute physical design, including floorplanning, synthesis, placement, clock tree synthesis, and routing.
- Drive timing closure and sign-off across corners and modes, including EM, IR drop, physical verification, and ECOs.
- Provide RTL feedback, improve PPA and shared flows, and oversee outsourced physical design work.
What they ask for
- Experience with physical design tools, flows, and methodology from RTL synthesis to GDSII sign-off.
- Back-end design and timing closure experience on advanced process nodes (5nm and below).
- Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) flows and sign-off tools such as PrimeTime, Tempus, or Voltus.
- Experience with UPF-based low-power design and scripting in Tcl, Python, or Perl.
Nice to have
- Familiarity with modern ML and LLM model architectures and AI tools for programming/coding.
- Startup experience or comfort working in fast-paced environments.
Pay
$200K – $375K (base salary)
Tools
Cadence, Innovus, Genus, Synopsys, Fusion Compiler, PrimeTime, Tempus, Voltus
AI focus
The company builds AI inference hardware; this role may benefit from familiarity with modern ML and LLM architectures and AI coding tools.
Model-written summary · the original posting is authoritative