Etched
Physical Design Engineer
$200K–$375K
San Jose · On-site · Full-time · Posted Aug 11, 2025
- Experience
- 5–10+ years of previous experience with physical design.
About the job
Own block-level physical design implementation and verification, close timing, optimize PPA, and improve design flows for ASIC products.
What you'll do
- Run physical design flows to close blocks and improve ASIC and CAD infrastructure.
- Collaborate with RTL designers on PPA, drive project-convergence dashboards, and optimize EDA tool flows.
- Own block-level closure and supervise outsourced physical-design work.
What they ask for
- Experience with physical design tools, flows, and methodology from RTL synthesis to GDSII sign-off.
- Back-end design and timing-closure experience on advanced process nodes (5nm and below).
- Experience with automated RTL-to-GDSII flows using Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler).
- Experience with sign-off tools and physical-design methodologies, including low-power design, verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, and IR drop and EM/antenna analysis.
Nice to have
- Familiarity with modern ML and LLM model architectures, AI coding tools, or Python or another scripting language.
- Startup experience or comfort working in fast-paced environments.
Pay
$200K – $375K USD base salary; significant equity amount not stated.
Tools
Cadence, Innovus, Genus, Synopsys, ICC2, Fusion Compiler, PrimeTime, Tempus
AI focus
The company builds inference-focused AI hardware; this role may benefit from familiarity with modern ML and LLM model architectures and AI coding tools.
Model-written summary · the original posting is authoritative