Etched
Physical Design Engineer - Full Chip Implementation
$200K–$375K
San Jose · On-site · Full-time · Posted Jul 23, 2026
- Experience
- 10+ years of previous experience with chip planning, top-level PD, and floorplanning.
About the job
Own full-chip physical design implementation from synthesis through GDSII, including timing closure, physical verification, signoff, and PPA optimization.
What you'll do
- Own full-chip clocking, top-level MMMC timing closure, constraints, and hierarchical timing budgets.
- Drive ECO closure and final timing signoff for tapeout.
- Own physical verification closure, debug violations, and build a repeatable tapeout-ready verification methodology.
What they ask for
- Experience with chip planning, top-level physical design, and floorplanning.
- Experience with top-level and full-chip closure on 5nm-and-below process nodes.
- Experience with automated RTL-to-GDSII flows using Cadence (Innovus, Genus) or Synopsys (Fusion Compiler).
- Experience with timing signoff tools, physical verification signoff, hierarchical timing budgeting, constraint management, and ECO closure.
Nice to have
- Familiarity with modern ML and LLM model architectures.
- Python or another scripting language; familiarity with AI tools for programming/coding.
Pay
$200K – $375K USD base salary
Tools
Cadence, Innovus, Genus, Synopsys, Fusion Compiler, PrimeTime, Tempus, Pegasus
AI focus
The company builds inference-focused AI hardware; familiarity with modern ML and LLM model architectures is a preferred qualification.
Model-written summary · the original posting is authoritative