Fortell
Physical Design Engineer
$150K–$250K
San Francisco Bay Area, CA, United States · Full-time · Posted Jul 6, 2026
- Experience
- 7+ years of hands-on physical design and implementation experience; preferred qualifications also state 7+ years in physical design roles and related activities.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
About the job
Executes and signs off physical design for custom ASIC partitions, bringing designs from RTL to silicon while improving implementation flows and methodologies.
What you'll do
- Run synthesis, place and route (PnR), and static timing analysis (STA); resolve implementation and signoff issues with cross-functional teams.
- Close EM/IR, and drive logical equivalence checking (LEC) and physical verification signoff for assigned partitions.
- Troubleshoot design-flow issues and help refine physical design methodologies, coordinating with methodology owners and EDA vendors.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
- 7+ years of hands-on physical design and implementation experience, including synthesis, PnR, timing convergence, and physical verification.
- Proficiency with EDA tools such as Innovus, Tempus, and Quantus, and deep understanding of physical design flows and methodologies.
Nice to have
- Experience with SoC design and implementation or sub-7nm technologies.
- TCL scripting skills for developing custom flows and methodologies using Cadence/Synopsys EDA tools.
Pay
USD 150K – 250K base salary
Tools
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
AI focus
The physical design work supports custom ASICs powering an AI-enabled hearing platform; no specific AI development work is stated.
Model-written summary · the original posting is authoritative