Fortell
Principal DFT Engineer
$160K–$300K
San Francisco Bay Area, CA, United States · Principal · Full-time · Posted Mar 2, 2026
About the job
Leads full-chip design-for-test architecture and implementation, supporting test coverage, silicon debug, and production testing for custom silicon.
What you'll do
- Develop and implement full-scan, boundary-scan, memory-test, scan-compression, MBIST, BIST, and JTAG structures.
- Generate and verify ATPG patterns, analyze coverage, and debug MBIST and gate-level simulation issues.
- Collaborate with engineering and test teams on DFT challenges, silicon bring-up, debug, and production testing.
Nice to have
- Experience developing DFT specifications and architectures for complex designs and debugging ATPG, MBIST, and coverage issues.
- Proficiency with Cadence Modus and Genus, and TCL scripting.
Pay
$160,000–$300,000 annually (base salary); $160K – $300K (base salary)
Tools
ATPG, JTAG, MBIST, Cadence Modus, Genus, TCL
Model-written summary · the original posting is authoritative